1. Field of the Invention
The present invention relates to high-speed and low power data decoding in communication systems, and to decoders providing such decoding. The present invention relates to semi-automated methods for exploration of data decoding methods, to approximations for data decoding methods and/or instruction sets delivered by such methods, to application specific instruction set processors (ASIPs) capable of executing instructions of such instruction sets, to systems for execution of decoding methods and to methods for executing decoding methods.
2. Description of the Related Technology
In digital communication systems, reliable transmission is achieved by means of channel coding, a class of forward error correction (FEC) techniques. Coding the information means adding redundancy to the bit stream at the transmitter side, so that it can be properly reproduced at the receiver side.
Nowadays, mobile devices are integrating an increasing variety of wireless communication and connectivity standards, each depicting a multitude of operation modes. This diversity, combined with the increasing cost of semiconductor, e.g. silicon, implementation claims for flexible implementations wherever possible.
A software defined radio (SDR) system is a radio communication system where components, such as e.g. mixers, filters, amplifiers, modulators/demodulators, detectors etc., that have typically been implemented in hardware are instead implemented using software on a processor of a personal computer or other embedded computing device. Significant amounts of signal processing are handed over to the processor, rather than being done using special-purpose hardware. The Tier-2 SDR approach, where the whole baseband functionality is run on a programmable architecture, is an attractive way to obtain the above flexibility. Great advances were recently booked in SDR for mobile applications. Multiple SDR processors have been proposed, covering most of the baseband processing with satisfactory performance and energy efficiency. In some cases, forward error correction is implemented on the same processor as the rest of the baseband.
More recent developments have been tackling high throughput communication standards such as IEEE 802.11n and 3GPP LTE. However, as it typically depicts a magnitude higher computation load, forward error correction (FEC) has been excluded from the scope of most of these high throughput solutions and lead to separate dedicated hardware accelerators. Lots of research is being carried out about efficient implementation of such hardware accelerators.
The number of advanced FEC options for broadband communication standard is, however, also growing rapidly. Besides 3GPP where convolutional turbo codes are used for a while, the IEEE adopted low-density parity-check (LDPC) coding schemes as optional for the third WLAN generation (IEEE 802.11n) as well as for fixed broadband wireless access (IEEE 802.16a) and their mobility extension (IEEE 802.16e). IEEE 802.16 also consider convolutional and block turbo codes as other optional schemes. Advanced forward error correction is also getting popular in broadcast standards. For instance, LDPC is used in DVB-S2/T2. Although these applications have a lower channel throughput, high throughput implementations are still required to enable multi-channel viewing and recording in set-top-boxes.
Flexibility is hence required for advanced FEC too. To address this need, recent contributions were looking at application specific instruction set processor (ASIP) implementations These solutions enable running different kind of turbo codes as well as Viterbi decoding on the same processor. In case of LDPC, advances were presented in offering flexibility by combining checknode processing with an interconnection network.
However, no application specific architecture has been presented yet that allows one to map both turbo and LDPC decoding at high throughput, with full memory architecture sharing, full data-path reuse and high energy efficiency.